1. Field of the Invention
The present invention relates to large scale arrays of transistors, and more particularly concerns an improved arrangement of active devices in a very large scale integrated circuit configured to maximize the advantages of high angle ion implantation.
2. Description of Related Art
Very large scale integrated circuit dies typically contain large numbers of submicron transistors manufactured by multi-step procedures that include the laying down of different layers of conductive and non-conductive materials, masking and selective removal of portions of deposited layers. Selected portions of the die are typically doped with impurities to provide areas of n-type and p-type regions and to form the active devices. Implantation of impurities by use of high angle ion implantation methods are known in the integrated circuit fabrication arts to provide a number of benefits.
Typically, very large scale integrated circuits are made with a central active region in which all of the central active devices are oriented in the same direction. Positioned around the periphery of the active region, usually on all four sides thereof, are rows of input output transistors. In prior art systems the input output devices are oriented in each of two mutually orthogonal directions, with the input output devices of the rows at the top and bottom of the active array, for example, being oriented in one direction and the input/output devices of the row at the left side and the row at the right side of the array being oriented in a perpendicular direction. Typically the input/output devices are oriented parallel to the edge of the integrated circuit die to which they are adjacent. With this input/output arrangement a quadrature ion implant is normally employed in order form the input/output devices. In quadrature high angle ion implantation the wafer on which the various arrays are being formed is tilted to the vertical by an angle on the order of greater than 0.degree. to about 60.degree., preferably 7.degree. to 45.degree. and a vertically directed beam of ions are directed at the wafer. Upon completion of a first ion implant, the wafer is turned 90.degree. and a second high angle ion implantation step is performed. The wafer is then again turned 90.degree. a third and a fourth time, each time performing a high angle implantation, to ensure that all sides of the variously oriented transistors are subject to symmetrical ion implantation and to ensure that no parts of the devices are effectively in the shadow of raised portions of the device.
Each ion implantation step requires a finite time, and thus increased time of production results. Additionally, high angle implantation directed at the side of an active device, instead of along a line drawn from a device source to a device drain, can cause degradation of electrical properties of the field oxide edge. The quadrature orientation of the input/output devices, however, typically results in at least some high angle implantation along undesirable orientations. Accordingly, it is an object of the present invention to provide a gate array layout that significantly improves high angle ion implantation procedures.